1. Field of the Invention
This invention relates to a thyristor and, more particularly, it relates to an improved GTO thyristor
2. Description of the Related Art
Conventionally, a GTO thyristor is turned off by drawing out the electric current within the device through a gate electrode directly fitted to the base layer of the device by means of a current-driven type drive device. Such a current-driven technique, however, requires the use of a gate circuit adapted to accommodate large electric power and hence of a large drive device.
A voltage control type GTO thyristor comprising an insulated gate such as an EST (emitter switched thyristor) has been proposed to bypass the above identified problem.
FIG. 19 of the accompanying drawings illustrates in cross section a known EST.
The EST comprises an n-base layer 83, a p-emitter layer 82 formed on one of the surface of the n-base layer 83, an anode electrode 81 disposed on the p-emitter layer 82, a p-base layer 84 selectively formed on the other surface of the n-base layer 83 and an n-emitter layer 85 selectively formed on the surface of the p-base layer 84, said semiconductor layers 82 through 85 providing this device with a thyristor portion through their pnpn structure.
A p.sup.+ -layer 86 and an n.sup.+ -layer 87 are formed side by side on the surface of the p-base layer 84 and a cathode electrode 88 is arranged to bridge the surface of the p.sup.+ -layer 86 and that of the n.sup.+ -layer 87. A gate electrode 90 is disposed on the p-base layer 84 to bridge the n.sup.+ -layer 87 and n-emitter layer 85 with a gate oxide film 89 interposed therebetween, said p-base layer 84, n-emitter layer 85, n.sup.+ -layer 87, gate oxide layer 89 and gate electrode 90 constituting an n-channel MOSFET (metal oxide semiconductor field effect transistor) Tr1.
Similarly, another gate electrode 80 is disposed on the n-emitter layer 85, the p-base layer 84 and the n-base layer 83 with an insulation film 79 interposed therebetween, said n-emitter layer 85, p-base layer 84, n-base layer 83, gate oxide film 79 and gate electrode 80 constituting another n-channel MOSFET Tr2.
A GTO thyristor having a configuration as described above is turned on by applying a positive voltage to the gate terminal G in relation to the cathode terminal K, while applying a forward voltage between the anode terminal A and the cathode terminal K.
As the voltages are applied, an n-channel ch1 is produced on the surface of the p-base layer 84 between the n.sup.+ -layer 87 and the n-emitter layer 85 while another n-channel ch2 is produced on the surface of the p-base layer 84 between the n-emitter layer 85 and the n-base layer 83 so that electrons may flow from the n.sup.+ -layer 87 to the n-emitter layer 85 by way of the first n-channel ch1 and from the n-emitter layer 85 to the n base layer 83 via the second n-channel ch2.
Thus, a base current takes place in a transistor constituted by a p-emitter layer 82, an n-base layer 83 and a p-base layer 84.
On the other hand, holes of the p-emitter layer 82 are made to flow from there to the p-base layer 84 through the n-base layer 83.
In other words, another base current takes place in another transistor constituted by an n-base layer 83, a p-base layer 84 and an n-emitter layer 85.
Consequently, the first transistor constituted by a p-base layer 82, an n-base layer 83 and a p-base layer 84 and the second transistor constituted by an n-base layer 83, a p-base layer 84 and an n-emitter layer 85 mutually amplify the respective collector currents of the other parties to turn on the thyristor.
The thyristor can be turned off by applying an negative voltage to the gate terminal G in relation to the cathode terminal K to turn off the MOSFET Tr1 and stop the supply of electrons to the n-emitter layer 85.
However, a thyristor of the above described type is accompanied by problems as described below.
As a flow of holes runs into the cathode electrode 88 through the p-base layer 84 under n.sup.+ -layer 87, the p-base layer 84 shows a voltage drop due to the resistance of the p-base layer 84.
The voltage drop forwardly biases the n.sup.+ -layer 87 and the p-base layer 84 so that electrons flow from the n.sup.+ -layer 87 into the n-base layer 83 by way of the p-base layer 84. Consequently, a parasitic thyristor PT constituted by the n.sup.+ -layer 87, the p-base layer 84, the n-base layer 83 and the p emitter layer 82 comes into existence and latches up the host thyristor HT. Since electric current flows through the parasitic thyristor, the current cannot be prevented from flowing through the device even when the host is turned off.
Additionally, the voltage drop turns on another parasitic transistor constituted by the n.sup.+ -layer 87, the p-base layer 84 and the n-emitter layer 85 to cause electrons to flow into the n-emitter layer 85 so that, again, the host thyristor constituted by the p-emitter layer 82, the n-base layer 83, the p-base layer 84 and the n-emitter layer 85 is forced to continue its operation after the gate is turned off.